The present invention relates generally to semiconductor devices; and more particularly, to the contact structures for semiconductor devices. Still more particularly, the present invention relates to a device and process that uses sidewall butted connection and silicide bridge connection for reducing structure count, complexity, and size.
One type of basic semiconductor device is the CMOS static random access memory (SRAM) which retains its memory state without refreshing as long as power is supplied to the cells. In a typical SRAM, the memory is stored as a voltage differential within a bistable cell constructed of two cross-coupled inverters. Data is written into or read from the cell through two pass gate transistors oppositely biased by a bit line, and a bit bar line, and controlled by a word line. Each inverter is composed of a P-channel metal-oxide-semiconductor (MOS) field-effect-transistor (PMOSFET) in series with an input/output (I/O) node, and an N-channel MOSFET (NMOSFET). The node of each inverter is connected to the gates of both transistors of the other inverter. An I/O transistor is connected from a bit line to the node of a first inverter. Another I/O transistor is connected from a bit line bar (always biased oppositely from the Bit line) to the node of a second inverter. In semiconductor memory designs, large memory count, stable data retention, and speed are valued. However, large memory count and complex structures add up to a large cell physical size, which results in higher fabrication expense and slower speed. As such, reducing structure count of contacts and their complexity is relevant.
Efficient integrated circuit chip layout of a standard six-transistor SRAM may minimize the area required. However, as the demand for more complex integrated circuits, smaller transistors and structures, and for faster and more reliable performance continues to grow, new approaches are needed. Even the contact structures occupy valuable area in memory cells. Therefore, reductions in contact count, complexity, and size are of paramount importance.
Silicon-on-insulator (SOI) is a structure of silicon structure in which a thin layer of insulating oxide is buried just below the top surface. A thin layer of single-crystal silicon above the oxide may then be used for the construction of semiconductor devices. These devices are typically isolated in individual islands of the aforesaid thin layer of single-crystal silicon. By constructing and separating circuit elements with no substrate connection, latch-ups may be avoided in CMOS devices. Also, junction capacitance may be reduced, thereby achieving higher speed.
For maximum density to be achieved in logic circuits and SRAM, the cells must be laid out in as small a size as possible. In nanometer technology, the SOI MOSFETs have been researched for high-speed, low-leakage and high-density products. In addition, SOI technology allows for a tighter design rule because of well isolation margins.
Desirable in the art of semiconductor devices are additional designs and cell layouts that utilize SOI technologies in tandem with other technologies to achieve reduction in contact count, complexity and size, thereby improving overall speed and performance.